The present invention relates to controllers for dynamic memories, and particularly to integrated circuits which control DRAM memory.
The disclosed preferred embodiments provide a DRAM controller which
.cndot. "serializes" and PA1 .cndot. "nonvolatizes" a bank of DRAMs, while PA1 .cndot. providing multi-generation flexibility, PA1 .cndot. providing refresh control which is totally transparent to the system, and PA1 .cndot. providing various overhead management functions.
To appreciate the interrelation and desirability of these features, and the specific innovative implementations used to achieve them, various general aspects of the DRAM art will first be reviewed.